In general, one or more electronic circuits, e.g. integrated circuits, dies, chips or integrated circuit structures, may be embedded into mold material to provide a chip embedding package, e.g. an embedded wafer level package (eWLB or eWLP), e.g. a fan-out wafer level package (FOWLP), and the like. In semiconductor processing, wafer level packaging (WLP) may be used for packaging an integrated circuit while the integrated circuit is still part of the wafer or while the integrated circuit is handled as a wafer. In contrast, individual integrated circuits (e.g. individual chips or dies) may be first singulated from the wafer and packaged subsequently in other packaging technologies, wherein the chips or dies may be packaged individually. Wafer level packaging or a wafer level package may be regarded as a chip-scale package (CSP), wherein the resulting package may be substantially of the same size as the die or chip. A wafer level package may include electrical contacts, e.g. solder lands, for electrically contacting the one or more electronic circuits embedded into the mold material of a wafer level package.